There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plane arrays. CCDs are often employed for image acquisition for small size imaging applications. CCDs are also capable of large formats with small pixel size and they employ low noise charge domain processing techniques. However, CCD imagers have a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays.
Because of the inherent limitations in CCD technology, there is an interest in complementary metal oxide semiconductor (CMOS) imagers for possible use as low cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.
A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photodiode, a photogate or a photoconductor overlying a doped region of a substrate for accumulating photo-generated charge in the underlying portion of the substrate.
In a conventional CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to a floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate. For photodiodes, image lag can be eliminated by completely depleting the photodiode upon readout.
CMOS image sensors of the type discussed above are generally known as discussed, for example, in Nixon et al., “256.times.256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S. Pat. Nos. 6,177,333 and 6,204,524 which describe operation of conventional CMOS imagers, the contents of which are incorporated herein by reference.
CMOS imagers have a number of advantages, including for example low voltage operation and low power consumption. CMOS imagers are also compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD since standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
Many conventional imagers have a photosensitive element formed just below a semiconductor substrate's surface at which circuitry is also formed. In a CMOS imager, for example, each pixel's photosensitive element typically includes a suitably doped region of semiconductor substrate, while the pixel's circuitry includes N-channel devices with gates on the substrate surface. At the periphery of the pixel array, circuitry for image readout and processing typically includes N-channel and P-channel devices with gates also on the substrate's surface.
Both the N-channel and the P-channel gates typically have insulating spacers at their sides, and the spacers act as masks for subsequent operations such as doping. The insulating spacers can be oxide, nitride, or an oxide/nitride sandwich structure. Conventionally, a single blanket spacer etch concurrently forms the spacers for the N-channel and P-channel devices by patterning an oxide layer. This etch removes the insulating layer from the photosensitive element and leaves the photosensitive element exposed to subsequent processes.
Photosensitive elements of CMOS imagers and other imagers are susceptible to various known defects, such as excessive dark current or other leakage and parasitic effects, crosstalk between pixels, and others. It would be advantageous to have improved methods for fabricating imaging devices, to reduce the risk of damage or defects in imager photosensitive elements. It would also be advantageous to have imagers that avoid such risks of damage or defects.